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december 2009 ? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg5842ja ? rev. 1.4.3 sg5842a/sg5842ja ? highly integrated green-mode pwm controller sg5842a/sg5842ja ? highly integrated green-mode pwm controller features ? green-mode pwm controller ? low startup current: 14a ? low operating current: 4ma ? programmable pwm frequency with hopping (sg5842ja) ? peak-current-mode control ? cycle-by-cycle current limiting ? synchronized slope compensation ? leading-edge blanking (leb) ? constant output power limit ? totem-pole output with soft driving ? v dd over-voltage protection (ovp) ? programmable over-temperature protection (otp) ? internal latch circuit (otp, ovp) ? internal open-loop protection ? v dd under-voltage lockout (uvlo) ? gate output maximum voltage clamp: 18v applications general-purpose switch-mode power supplies and flyback power converters, including: ? notebook power adapters ? open-frame smps description the highly integrated sg5842a/ja series of pwm controllers provides several features to enhance the performance of flyback converters. to minimize standby power consumption, a proprietary green-mode function provides off-time modulation to continuously decrease the switching frequency at light-load conditions. to avoid acoustic-noise problems, the minimum pwm frequency set above 22khz. this green-mode function enables the power supply to meet international power conservation requirements. to further reduce power consumption, sg5842a/ja is manufactured using the bicmos process. this allows a low startup current, around 14a, and an operating current of only 4ma. as a result, a large startup resistance can be used. the sg5842a/ja built-in synchronized slope compensation achieves stable peak-current-mode control. sg5842ja integrates a frequency-hopping function that helps reduce emi emission of a power supply with minimum line filters. sg5842a/ja provides many pr otection functions. in addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety should an open-loop or output short-circuit failure occur. pwm output is disabled until v dd drops below the uvlo lower limit, then the controller starts again. as long as v dd exceeds about 24v, the internal ovp circuit is triggered. an external ntc thermistor can be applied for over- temperature protection. sg5842a/ja is available in an 8-pin dip or sop package.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg582ja ? rev. 1.4.3 2 sg5842a/sg5842ja ? highly integrated green-mode pwm controller ordering information part number operating temperature range eco status package otp latch ovp latch frequency hopping sg5842jasz -40c to +105c rohs 8-pin small outline package (sop) yes yes yes sg5842jadz -40c to +105c rohs 8-pin dual inline package (dip) yes yes yes sg5842jasy -40c to +105c green 8-pin small outline package (sop) yes yes yes sg5842asz (preliminary) -40c to +105c rohs 8-pin small outline package (sop) yes yes no SG5842ASY (preliminary) -40c to +105c green 8-pin small outline package (sop) yes yes no for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/com pany/green/rohs_green.html . application diagram figure 1. application diagram
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg582ja ? rev. 1.4.3 3 sg5842a/sg5842ja ? highly integrated green-mode pwm controller f - fairchild logo z- plant code x- 1 digit year code y- 1 digit week code tt: 2 digits die run code t: package type (s=sop, d=dip) p: y: green package m: manufacture flow code h: j = with frequency hopping null = without frequency hopping t : d = dip, s = sop p: z = lead free null = regular package xxxxxxxx: wafer lot y : year; ww : week v : assembly location block diagram figure 2. function block diagram marking information figure 3. top mark zxytt sg5842ha tpm marking for sg5842jasz (pb-free) marking for sg5842jadz (pb-free) marking for sg5842asz (pb-free) marking for sg5842adz (pb-free) marking for sg5842jasy (green-compound) marking for SG5842ASY (green-compound) sg5842 h a tp xxxxxxxxywwv
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg582ja ? rev. 1.4.3 4 sg5842a/sg5842ja ? highly integrated green-mode pwm controller pin configuration figure 4. pin configuration pin definitions pin # name description 1 gnd ground 2 fb the signal from the external compensation circuit is fed into this pin. the pwm duty cycle is determined in response to the signal from this pi n and the current-sense signal from pin 6. if fb voltage exceeds the threshold, the internal pr otection circuit disables pwm output after a predetermined delay time. 3 vin for startup, this pin is pulled high to the rect ified line input via a resistor. since the startup current requirement is very small, a large star tup resistance can be used to minimize power loss. 4 ri a resistor connected from the ri pin to gnd prov ides a constant current source. this determines the center pwm frequency. increasing the re sistance reduces pwm frequency. using a 26k ? resistor results in a 65khz center pwm frequency. 5 rt for over-temperature protection. an external ntc thermistor is connected from this pin to the gnd pin. the impedance of the ntc decreases at high temperatures. once the voltage of the rt pin drops below a fixed limit, pwm output is latched off. 6 sense current sense. the sensed voltage is used fo r peak-current-mode control and cycle-by-cycle current limiting. 7 vdd power supply. the internal protec tion circuit disables pwm output if v dd is over-voltage. 8 gate the totem-pole output driver for the power mosfet, which is internally clamped below 18v.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg582ja ? rev. 1.4.3 5 sg5842a/sg5842ja ? highly integrated green-mode pwm controller absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v vdd supply voltage (1) 30 v v vin input terminal 30 v v fb input voltage to fb pin -0.3 7.0 v v sense input voltage to sense pin -0.3 7.0 v v rt input voltage to rt pin -0.3 7.0 v v ri input voltage to ri pin -0.3 7.0 v p d power dissipation (t a < 50c ) dip 800 mw sop 400 ja thermal resistance (junction-to-air) dip 82.5 c/w sop 141 t j operating junction temperature -40 +125 c t stg storage temperature range -55 +150 c t l lead temperature (wave soldering or infrared, 10 seconds) +260 c esd electrostatic discharge capability human body model, jesd22-a114 3 kv charged device model, jesd22-c101 1 notes: 1. all voltage values, except differential voltage, are given with respect to gnd pin. 2. stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit t a operating ambient temperature -20 +85 c
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg582ja ? rev. 1.4.3 6 sg5842a/sg5842ja ? highly integrated green-mode pwm controller electrical characteristics v dd =15v and t j =t a = -40~125 c, unless otherwise noted. symbol parameter conditions min. typ. max. units v dd section v dd-op continuously operating voltage 20 v v dd-on start threshold voltage 15.5 16.5 17.5 v v dd-off minimum operation voltage 9.5 10.5 11.5 v i dd-st startup current v dd =v dd-on ?0.16v 14 30 a i dd-op operating supply current v dd =15v, r i =26k ? , gate=open 4 5 ma v dd-ovp v dd over-voltage protection 23.2 24.2 25.2 v t d-ovp v dd over-voltage protection debounce time r i =26k ? 100 s i dd-h holding current after ovp/otp latchup v dd =5v 40.0 52.5 65.0 a ri section ri nor r i operating range 15.5 36.0 k ? ri max maximum r i value for protection 230 k ? ri min minimum r i value for protection 10 k ? oscillator section f osc normal pwm frequency center frequency r i =26k ? 62 65 68 khz hopping range r i =26k ? sg5842ja only 3.7 4.2 4.7 t hop hopping period r i =26k ? sg5842ja only 3.9 4.4 4.9 ms f osc-g green-mode minimum frequency r i =26k ? 18 22 25 khz f dv frequency variation vs. v dd deviation v dd =11.5v to 20v 5 % f dt frequency variation vs. temperature deviation t a =-20 to 85 c 5 % feedback input section a v fb input to current comparator attenuation 1/4.5 1/4.0 1/3.5 v/v z fb input impedance 4 7 k ? v fb-open output high voltage fb pin open 5.5 v v fb-olp fb open-loop trigger level 5.0 5.4 v t d-olp fb open-loop protection delay r i =26k ? 50 56 62 ms v fb-n green-mode entry fb voltage r i =26k ? 1.9 2.1 2.3 v v fb-g green-mode ending fb voltage r i =26k ? v fb-n -0.5 v continued on the following page?
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg582ja ? rev. 1.4.3 7 sg5842a/sg5842ja ? highly integrated green-mode pwm controller electrical characteristics (continued) v dd = 15v and t j =t a = -40~125 c, unless otherwise noted. figure 5. v fb vs. pwm frequency symbol parameter conditions min. typ. max. units current sense section z sense input impedance 12 k ? v sthfl current limit flatten threshold voltage 0.85 0.90 0.95 v v sthva current limit valley threshold voltage v sthfl ?v sthva 0.22 v dcy saw duty cycle of saw limit maximum duty cycle 45 % t pd propagation delay to gate output r i =26k ? 150 200 ns t leb leading-edge blanking time r i =26k ? 200 270 350 ns gate section dcy max maximum duty cycle 60 65 70 % v gate-l output voltage low v dd =15v, i o =50ma 1.5 v v gate-h output voltage high v dd =12.5v, i o =-50ma 7.5 v t r rising time v dd =15v, c l =1nf 150 250 350 ns t f falling time v dd =15v, c l =1nf 30 50 90 ns i o peak output current v dd =15v, gate=6v 230 ma v gate- clamp gate output clamping voltage v dd =20v 18 19 v rt section i rt output current of rt pin r i =26k ? 67 70 73 a v rtth over-temperature protection threshold voltage 1.015 1.050 1.085 v t d-otp over-temperature debounce r i =26k ? 60 100 140 s
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg582ja ? rev. 1.4.3 8 sg5842a/sg5842ja ? highly integrated green-mode pwm controller performance characteristics 10 14 18 22 26 30 -40 -25 -10 5 20 35 50 65 80 95 110 125 i dd-st (a) temperature c 2.5 3.0 3.5 4.0 4.5 5.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 i dd-op (ma) temperature c figure 6. startup current ( idd-st ) vs. temperature figure 7. operating supply current (i dd-op ) vs. temperature 0 3 6 9 12 15 12 13 14 15 16 17 18 19 20 21 22 23 24 v dd voltage (v) i d d - o p ( m a ) gate=ope n gate=1000pf 15.5 16.0 16.5 17.0 17.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 v d d - o n ( v ) temperature c figure 8. operation current (i dd-op ) vs. v dd operation figure 9. start threshold (v dd-on ) vs. temperature 9.5 10.0 10.5 11.0 11.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 v d d - o f f ( v ) temperature c 62 63 64 65 66 67 68 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature c f o s c ( k h z ) figure 10. minimum operating voltage (v dd-off ) vs. temperature figure 11. pwm frequency (f osc ) vs. temperature
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg582ja ? rev. 1.4.3 9 sg5842a/sg5842ja ? highly integrated green-mode pwm controller performance characteristics (continued) 60 62 64 66 68 70 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature c d c y m a x ( % ) 1.015 1.025 1.035 1.045 1.055 1.065 1.075 1.085 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature c v r t t h ( v ) figure 12. maximum duty cycle (dcy max ) vs. temperature figure 13. trigger voltage for over-temperature protection (v rtth ) vs. temperature 67 68 69 70 71 72 73 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature c i r t ( a ) figure 14. output current of rt pin (i rt ) vs. temperature
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg582ja ? rev. 1.4.3 10 sg5842a/sg5842ja ? highly integrated green-mode pwm controller functional description startup current the typical startup current is only 14a, which allows a high-resistance, low-wattage startup resistor to be used to minimize power loss. a 1.5m ? /0.25w startup resistor and a 10f/25v v dd hold-up capacitor are sufficient for an ac/dc adapter with a universal input range. operating current the required operating current has been reduced to 4ma. this results in higher efficiency and reduces the v dd hold-up capacitance requirement. green-mode operation the proprietary green-mode function provides off-time modulation to continuously decrease the pwm frequency under light-load conditions. to avoid acoustic noise problems, the minimum pwm frequency is set above 22khz. this green-mode function dramatically reduces power consumption under light-load and zero- load conditions. power supplies using this controller can meet even the strictest international standby power regulations. oscillator operation a resistor connected from the ri pin to the gnd pin generates a constant current source for the controller. this current is used to determine the center pwm frequency. increasing the resistance reduces pwm frequency. using a 26k ? resistor, r i , results in a corresponding 65khz pwm frequency. the relationship between r i and the switching frequency is: (khz) ) (k r 1690 i pwm f = (1) the range of the pwm oscillation frequency is designed as 47khz ~ 109khz. sg5842ja also integrates a frequency hopping function internally. the frequency variation ranges from around 62khz to 68khz for a center frequency of 65khz. the frequency hopping function helps reduce emi emission of a power supply with minimum line filters. leading-edge blanking (leb) each time the power mosfet is switched on, a turn-on spike occurs at the sense resistor. to avoid premature termination of the switching pulse, a leading-edge blanking time is built in. during this blanking period, the current-limit comparator is disabled and cannot switch off the gate drive. under-voltage lockout (uvlo) the turn-on/turn-off thresholds are fixed internally at 16.5v/10.5v. to enable a sg5842a/ja controller during startup, the hold-up capacitor must first be charged to 16.5v through the startup resistor. the hold-up capacitor continues to supply v dd before energy can be delivered from the auxiliary winding of the main transformer. v dd must not drop below 10.5v during this startup process. this uvlo hysteresis window ensures that the hold-up capacitor can adequately supply v dd during startup. gate output / soft driving the sg5842a/ja bicmos output stage is a fast totem- pole gate driver. cross-conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. the output driver is clamped by an internal 18v zener diode to protect the power mosfet transistors from harmful over-voltage gate signals. a soft-driving waveform is implemented to minimize emi. slope compensation the sensed voltage across the current sense resistor is used for peak-current-mode control and cycle-by-cycle current limiting. the built-in slope compensation function improves power supply stability and prevents peak-current-mode control from causing sub-harmonic oscillations. within every switching cycle, the sg5842a/ja controller produces a positively sloped, synchronized ramp signal. constant output power limit when the sense voltage across the sense resistor, r s , reaches the threshold voltage, around 0.85v; the output gate drive is turned off after a small delay, t pd . this delay introduces additional current proportional to t pd ? v in / l p . the delay is nearly constant regardless of the input voltage v in. higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. to compensate this variation for a wide ac input range, a sawtooth power-limiter (saw limiter) is designed to solve the unequal power-limit problem. the saw limiter is designed as a positive ramp signal (v limit_ramp ) fed to the inverting input of the ocp comparator. this results in a lower current limit at high-line inputs than at low- line inputs. v dd over-voltage protection (ovp) v dd over-voltage protection is built in to prevent damage due to abnormal conditions. once the v dd voltage is over the v dd over-voltage protection voltage (v dd-ovp ) and lasts for t d-ovp , the pwm pulse is latched off. the pwm pulses stay latched off until the power supply is unplugged from the mains outlet.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg582ja ? rev. 1.4.3 11 sg5842a/sg5842ja ? highly integrated green-mode pwm controller functional description (continued) limited power control the fb voltage increases every time the output of the power supply is shorted or overloaded. if the fb voltage remains higher than a built-in threshold longer than t d- olp , pwm output is turned off. as pwm output is turned off, the supply voltage v dd begins decreasing. ) (k i r 154 . 2 (ms) t olp - d = (2) when v dd goes below the turn-off threshold (eg. 10.5v), the controller is totally shut down. v dd is charged up to the turn-on threshold voltage of 16.5v through the startup resistor until pwm output is restarted. this protection f eature remains activated as long as the overloading condition persists. this prevents the power supply from overheating due to overloading conditions. protection latch circuit the built-in latch function provides a versatile protection feature that does not require external components (see ordering information for a detailed description) . to reset the latch circuit, disconnect the ac line voltage of the power supply. thermal protection an external ntc thermistor can be connected from the rt pin to ground. a fixed current, i rt , is sourced from the rt pin. because the impedance of the ntc decreases at high temperatures, when the voltage of the rt pin drops below 1.05v, pwm output is latched off. the rt pin output current is related to the pwm frequency programming resistor r i . noise immunity noise from the current sense or the control signal may cause significant pulse width jitter, particularly in continuous-conduction mode. slope compensation helps alleviate this problem. good placement and layout practices should be followed. avoid long pcb traces and component leads. compensation and filter components should be located near the sg5842a/ja. increasing the power-mos gate resistance is advised.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg5842ja ? rev. 1.4.3 12 sg5842a/ja ? highly integrated green-mode pwm controller reference circuit 1 2 3 cn1 r1 c2 2 1 + c4 r2 r5 c3 2 1 3 4 bd1 2 1 d2 1 2 3 q2 r8 gnd 1 fb 2 vin 3 ri 4 rt 5 sense 6 vdd 7 gate 8 u1 sg5842a/ja 1 2 4 3 u2 c6 r4 1 3 2 q1 2 1 + c7 2 1 d4 r9 r16 r13 r15 r14 r11 c10 2 1 + c9 vz1 c1 1 2 3 4 l2 c11 r7 t1 r10 ther2 r3 c5 1 2 3 4 l1 r12 2 1 + c8 2 1 d3 a k r u3 vo+ 1 2 l3 tr1 d1 r6 vo+ figure 15. reference circuit bom reference component reference component bd1 bd 4a/600v q2 mos 7a/600v c1 xc 0.68f/300v r1, r2, r5, r7 r 470k 1/4w c2 xc 0.1f/300v r3 r 100k 1/2w c3 cc 0.01f/500v r4 r 47 1/4w c4 ec 120/400v r6 r 2k 1/8w c5 yc 222p/250v r8 r 0.3 2w c6 cc 1000pf/100v r9 r 33k 1/8w c7 ec 1000f/25v r10 r 4.7k 1/8w c8 ec 470f/25v r11 r 470 1/8w c9 ec 10f/50v r12 r 0 1/8w c10 cc 222pf/50v r13 r 4.7k 1/8w c11 cc 470pf/50v r14 r 154k 1/8w 1% d1 led r15 r 39k 1/8w 1% d2 diode byv95c r16 r 100 m 1/8w d3 tvs p6ke16a ther2 thermistor ttc104 d4 diode fr103 t1 transformer (600h-pq2620) f1 fuse 4a/250v u1 ic sg5842a/ja l1 choke (900h) u2 ic pc817 l2 choke (10mh) u3 ic tl431 l3 inductor (2h) vz1 vz 9g q1 diode 20a/100v
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg5842ja ? rev. 1.4.3 13 sg5842a/ja ? highly integrated green-mode pwm controller physical dimensions 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge figure 16. 8-pin, small outline package (sop) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg5842ja ? rev. 1.4.3 14 sg5842a/ja ? highly integrated green-mode pwm controller physical dimensions (continued) 5.08 max 0.33 min 2.54 7.62 0.56 0.355 1.65 1.27 3.683 3.20 3.60 3.00 6.67 6.096 9.83 9.00 7.62 9.957 7.87 0.356 0.20 notes: unless otherwise specified a) this package conforms to jedec ms-001 variation ba b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. d) dimensions and toleranc es per asme y14.5m-1994 8.255 7.61 e) drawing filename and revsion: mkt-n08frev2. (0.56) figure 17. 8-pin, dual inline package (dip) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com sg5842a/sg5842ja ? rev. 1.4.3 15 sg5842a/ja ? highly integrated green-mode pwm controller

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